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PIP212-12M
DC-to-DC converter powertrain
Rev. 02 -- 2 March 2005 Preliminary data sheet
1. General description
The PIP212M-12M is a fully optimized powertrain for high current high frequency synchronous buck DC-to-DC applications. The PIP212M-12M replaces two power MOSFETs, a Schottky diode and a driver IC, resulting in a significant increase in power density. The integrated solution allows for optimization of individual components and greatly reduces the parasitics associated with conventional discrete solutions, resulting in higher system efficiencies at higher frequency operation.
2. Features
s s s s s s s s s s s s s s s Input conversion range from 3.3 V to 16 V Output voltages from 0.8 V to 6 V Capable of up to 30 A maximum output current Operating frequency up to 1 MHz Peak system efficiency > 90 % at 500 kHz Automatic Dead-time Reduction (ADR) for maximum efficiency Internal thermal shutdown Auxiliary 5 V output Power ready output flag Power sequencing functions Fault flag for lost phase detection Internal 6.5 V regulator for efficient gate drive Compatible with single and multi-phase PWM controllers Internal boost switch for high efficiency and low noise Low-profile, surface-mounted package (8 mm x 8 mm x 0.85 mm)
3. Applications
s s s s s High-current DC-to-DC point-of-load converters Small form-factor voltage regulator modules Microprocessor and memory voltage regulators Intel(R) compatible VRM (VRM9 and VRM10) Intel(R) Driver MOS (DrMOS) compatible
Philips Semiconductors
PIP212-12M
DC-to-DC converter powertrain
4. Ordering information
Table 1: Ordering information Package Name PIP212-12M HVQFN56 Description Version plastic thermal enhanced very thin quad flat package; no leads; SOT684-4 56 terminals; body 8 x 8 x 0.85 mm Type number
5. Block diagram
CBP 5 CBN VDDO 10 8, 11 to 20
PIP212-12M
VDDC VDDG_EN VDDG REG5V 4 2 3 54 5 V REG 5V 56 5V
30 k
6.5 V REG
INTERNAL 5 V REG
UVLO
BOOST SWITCH
upper driver
VI
42 to 50 CONTROL LOGIC AND DEAD-TIME CONTROL VDDG
VO
OTP
DISABLE
55
PRDY
53
AIS
52
lower driver
signal ground power ground
1, 7, 51 VSSC
22 to 41
03ao37
VSSO
A bootstrap switch is integrated into the design of the PIP212-12M between VDDC and CBN
Fig 1. Block diagram
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6. Pinning information
6.1 Pinning
55 DISABLE
54 REG5V
53 PRDY
51 VSSC
52 AIS
50 VO
49 VO
48 VO
47 VO
46 VO
45 VO
44 VO
terminal 1 index area VSSC VDDG_EN VDDG VDDC CBP n.c VSSC VDDO n.c. 1 2 3 4 5 6 7 8 9
43 VO 42 VO 41 VSSO 40 VSSO 39 VSSO 38 VSSO 37 VSSO 36 VSSO 35 VSSO 34 VSSO 33 VSSO 32 VSSO 31 VSSO 30 VSSO 29 VSSO VSSO 28
03ao38
56 VI
VSSC PAD 1
PIP212-12M
CBN 10 VDDO 11 VDDO 12 VDDO 13 VDDO 14 VDDO 15 VDDO 16
VO PAD 3 VDDO PAD 2
VDDO 17
VDDO 18
VDDO 19
VDDO 20
VO_SENSE 21
VSSO 22
VSSO 23
VSSO 24
VSSO 25
VSSO 26
Transparent top view
Fig 2. Pin configuration
6.2 Pin description
Table 2: Symbol VDDC VDDO VSSC VSSO VI VO Pin description Pin 4 1, 7, 51, pad 1 22 to 41 56 42 to 50, pad 3 Type Description I O O I O O control circuit supply voltage output stage supply voltage control circuit ground output stage (supply) ground pulse width modulated input output voltage sense connection to VO often required by PWM for current sensing connection for bootstrap capacitor connection for bootstrap capacitor enables internal 6.5 V regulator for VDDG gate drive supply voltage indicates the switching status of VO (open drain) indicates that VDDC is above the UVLO level (open drain)
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8, 11 to 20, pad 2 I
VO_SENSE 21 CBP CBN VDDG_EN VDDG AIS PRDY
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Pin description ...continued Pin 54 55 6, 9 Type Description O I/O 5 V regulated supply output disable driver function (active LOW) not connected
Table 2: Symbol REG5V DISABLE n.c.
7. Functional description
7.1 Basic operation
conversion supply control circuit supply
VDDG REG5V PWM input VI
VDDC
VDDO CBP
100 nF
PIP212-12M CBN
VO VSSO power ground
Lout output
DISABLE VSSC signal ground
Cout
03ao39
Fig 3. Simplified functional block diagram of a synchronous DC-to-DC converter output stage
The PIP212-12M combines two MOSFET transistors and a MOSFET driver in a thermally enhanced low inductance package for use in high frequency and high efficiency synchronous buck DC-to-DC converters; see Figure 3. The two MOSFETs are connected in a half bridge configuration between VDDO and VSSO. The mid point of the two transistors is VO which is connected to the output of a DC-to-DC converter via an inductor. A logic HIGH signal on the VI pin causes the lower MOSFET to be switched off and the upper MOSFET to be switched on. Current will then flow from the supply (VDDO), through the upper MOSFET and the inductor (Lout) to the output. A logic LOW signal on the VI pin causes the upper MOSFET to be turned off and the lower MOSFET to be switched on. Current then flows from the power ground (VSSO), through the lower MOSFET and the inductor (Lout), to the output. The output voltage is determined by the ratio of time that the upper and lower MOSFETs conduct.
7.2 Undervoltage Lockout (UVLO)
The UVLO function ensures the correct operation of the control circuit during a power-up and power-down sequence. Power to the control circuit is provided by the VDDC pin. This voltage is internally monitored to ensure that if VDDC is below the UVLO threshold, the DISABLE pin is internally pulled LOW and both MOSFETs are off. This is indicated by the power ready (PRDY) flag, an open drain output that is pulled LOW whenever VDDC is below the UVLO threshold.
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7.3 Boost switch
The gate drive to the upper MOSFET is provided by a bootstrap capacitor (typically 100 nF) that is placed between the CBP and CBN pins. This capacitor is charged via an internal boost switch to a voltage within a few millivolts of VDDC up to a maximum of 12 V (this is to prevent excessive gate charge losses when VDDC > 12 V). The upper MOSFET will be switched according to PWM input once the boost capacitor voltage is above 4.3 V. When ever the voltage is below 2.7 V, the upper MOSFET will remain off.
7.4 VDDG regulator
The gate drive to the lower MOSFET is provided by the VDDG pin. A 1 F capacitor should be connected between this pin and VSSC. For minimum power loss within the PIP212-12M, an external power supply of between 5 V and 12 V should be connected to this pin. The optimum value for this voltage is dependent on the application but in the majority of cases a 5 V supply is recommended; see Figure 11. In cases where the VDDG maximum voltage will not be exceeded, the VDDG capacitor can be omitted by connecting the VDDG and VDDC pins; see Figure 13. When VDDC is connected to a supply greater than 9 V, an internal 6.5 V regulator connected to VDDG can be used to provide the gate drive for the lower MOSFET; see Figure 12. The VDDG regulator is enabled by leaving the VDDG_EN pin open resulting in this pin being pulled internally to 5 V. If an external supply is to be connected to VDDG then the VDDG_EN pin must be connected to VSSC to disable the internal VDDG regulator.
Table 3: VDDG_EN Open circuit VSSC VDDG biasing VDDG internal 6.5 V regulator used (VDDC > 9 V) connection to external supply required
7.5 3-state function
If the input to VI from the PWM controller becomes high impedance, then the VI input is driven to 2.5 V by an internal voltage divider. A voltage on the VI pin that is in-between the VIH and VIL levels and present for longer than td(3-state), causes both MOSFETs to be turned off. Normal operation commences once the VI input is outside this window for longer than td(3-state).
7.6 Automatic Dead-time Reduction (ADR)
Protection against cross-conduction (shoot-through) is achieved via the insertion of a delay (or dead-time) between the switching off of one MOSFET and the switching on of the other MOSFET. The automatic dead-time reduction feature continuously monitors the body diode of the lower MOSFET adjusting the dead-time to minimize body diode conduction. This reduces power loss in both the upper and lower MOSFETs due to the reduction in body diode conduction and reverse recovery charge. The lower power dissipation leads to higher system efficiency and enables higher frequency operation.
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7.7 Over Temperature Protection (OTP)
Protection against over temperature is provided by an internal thermal shutdown incorporated into the control circuit. When the control circuit die temperature exceeds the upper thermal trip level, both MOSFETs are switched off and the internal VDDG regulator disabled. This state continues until the die temperature falls below the lower trip temperature. This function is only operational when VDDC is above the UVLO level.
7.8 Am I Switching (AIS)
The AIS flag is designed for use with lost phase detection circuitry. During normal operation (i.e. when PRDY and DISABLE are HIGH and VI is either HIGH or LOW), the AIS pin is pulled LOW if no voltage transients have been detected on the VO pin for a period of approximately 40 s. If DISABLE is LOW or the driver is in 3-state mode, the AIS pin will become floating (open drain) irrespective of any previous state. False signals during start-up are prevented by activating this function approximately 200 s after either the DISABLE pin becoming HIGH or the driver leaving the 3-state mode.
7.9 Disable
This is the disable or enable function of the driver. Pulling the DISABLE pin LOW switches off both MOSFETs, disables the REG5V output, and makes the AIS flag open drain. This pin is internally pulled LOW whilst VDDC remains below the UVLO threshold. Once VDDC exceeds the UVLO threshold, this pin is pulled HIGH by an internal resistor. In this way the driver will enable itself unless there is an external pull down. In multiphase applications, connecting the DISABLE pins of multiple PIP212-12M devices together will ensure that all devices will only become enabled when the voltage on the VDDC pins of all of the devices has exceeded the UVLO threshold; see Figure 10.
7.10 Reg5V
This function provides a low current regulated 5 V output voltage suitable for providing power to a PWM controller. It is operational when both PRDY and DISABLE are HIGH. Operation as a 5 V power supply is only guaranteed when VDDC is > 7 V. This pin can also be used as part of an enable function for a PWM controller; this ensures that the PWM is enabled only when the PIP212-12M is fully operational (i.e. both PRDY and DISABLE are HIGH).
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8. Limiting values
Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDC VDDO VI VDDG VO VCB IO(AV) IORM VPRDY VDISABLE VREG5V VAIS Ptot Tstg Tj
[1] [2]
Parameter control circuit supply voltage output stage supply voltage input voltage gate drive supply voltage output voltage bootstrap capacitor voltage average output current repetitive peak output current power ready voltage at pin PRDY driver enable voltage at pin DISABLE 5 V regulated supply output voltage at pin REG5V output voltage at pin AIS total power dissipation storage temperature junction temperature
Conditions
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
Max +15 +24 +12.6 +12.6 VO + 15 30 60 +12.6 +12.6 +12.6 +12.6 25 12 +150 +150
Unit V V V V V A A V V V V W W C C
VDDO + 0.5 V
VDDC = 12 V; Tpcb 90 C; fi = 1 MHz VDDC = 12 V; tp 10 s
[1]
-0.5 -0.5 -0.5 -0.5
Tpcb = 25 C Tpcb = 90 C
[2] [2]
-55 -55
Pulse width and repetition rate limited by maximum value of Tj. Assumes a thermal resistance from junction to printed-circuit board of 5 K/W.
9. Thermal characteristics
Table 5: Symbol Rth(j-mb) Thermal characteristics Parameter thermal resistance from junction to mounting base Conditions device tested with upper and lower MOSFETs in series Min Typ 3 Max 5 Unit K/W
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10. Characteristics
Table 6: Characteristics VDDC = 12 V; Tj = 25 C unless otherwise specified. Symbol VDDC Vth(UVLO) VIH VIL ILI IDDC Parameter control circuit supply voltage Conditions 25 C Tj 150 C turn off HIGH-level input voltage LOW-level input voltage input leakage current control circuit supply current 0 V VI 5 V fi = 0 Hz, VI = 0 V fi = 500 kHz, VDDG_EN = open fi = 500 kHz, VDDG_EN = ground VDDG VREG5V IREG5V Vth(en) Vth(dis) Totp Totp(hys) Ptot gate driver supply voltage 5 V regulated supply output voltage at pin REG5V 5 V regulated supply output current from pin REG5V enable threshold voltage at pin DISABLE disable threshold voltage at pin DISABLE over temperature trip point over temperature trip hysteresis total power dissipation VDDO = 12 V; IO(AV) = 25 A; VO = 1.3 V; Tpcb = 90 C; fi = 500 kHz fi = 1 MHz Dynamic characteristics td(on)(IH-OH) td(off)(IL-OL) td(3-state)
[1]
[1] [1]
Min 6 4.1 3.75 3.3 1.4 6 4.5 165 -
Typ 12 4.2 3.9 3.5 1.5 170 8.2 50 12 6.5 5.0 24.0 3.1 1.6 15
Max 14 4.4 4.0 3.7 1.6 7 5.5 180 -
Unit V V V V V A mA mA mA V V mA V V C C
Static characteristics undervoltage lockout threshold voltage turn on
IL = 65 mA IL = 10 mA VREG5V = 4.5 V VDDC > 4.5 V VDDC > 4.5 V
-
4.5 5.8 100
85 45 -
W W ns ns ns
turn-on delay time input HIGH to output HIGH turn-off delay time input LOW to output LOW 3-state delay time
VDDO = 12 V; IO(AV) = 12.5 A
If the input voltage remains between VIH and VIL (2.5 V typ) for longer than td(3-state), then both MOSFETs are turned off.
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10 Ptot (W) 8
003aaa833
1.3 a 1.2
003aaa834
6 1.1 4 1.0 2
0 0 10 20 IO (A) 30
0.9 0 4 8 12 16 VDDO (V)
VDDC = 12 V; VDDO = 12 V; VO = 1.3 V; fi = 1 MHz
VDDC = 12 V; VO = 1.3 V; fi = 1 MHz; IO(AV) = 25 A
P tot a = ---------------------------------------P tot ( V = 12 V)
DDO
Fig 4. Total power dissipation as a function of average output current; typical values
003aaa835
Fig 5. Normalized power dissipation as a function of output stage supply voltage; typical values
003aaa836
1.8 b 1.6
1.2
c
1.0 1.4
1.2 0.8 1.0
0.8 0 2 4 VO (V) 6
0.6 200
400
600
800 f (kHz)
1000
VDDC = 12 V; VDDO = 12 V; fi = 1 MHz; IO(AV) = 25 A
VDDC = 12 V; VDDO = 1.3 V; VO = 1.3 V; IO(AV) = 25 A
P tot b = ----------------------------------P tot ( V = 1.3 V )
O
P tot c = -----------------------------------P tot ( f = 1 MHz )
i
Fig 6. Normalized power dissipation as a function of output voltage; typical values
Fig 7. Normalized power dissipation as a function of input frequency; typical values
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1.3 d 1.2
003aaa837
1.3 e 1.2
003aaa838
1.1
1.1
1.0
1.0
0.9 6 8 10 12 VDDC (V) 14
0.9 4 6 8 10 12 VDDG (V)
VDDO = 12 V; VO = 1.3 V; fi = 1 MHz; IO(AV) = 25 A
VDDC = 12 V; VDDO = 12 V; fi = 1 MHz; IO(AV) = 25 A
P tot d = ---------------------------------------P tot ( V = 12 V )
DDC
P tot e = -------------------------------------P tot ( V = 5 V)
DDG
Fig 8. Normalized power dissipation as a function of control circuit supply voltage; typical values
Fig 9. Normalized power dissipation as a function of gate drive supply voltage; typical values
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11. Application information
11.1 Typical application
conversion supply control circuit supply
10 1 F 1 F
22 F (4x)
VDDG REG5V VI
100 nF
VDDC
VDDO CBP
100 nF
PIP212-12M CBN
VO VSSO VSSC
360 nH 100 F (2x)
DISABLE
10 1 F 1 F
22 F (4x)
VDDG REG5V VI
VDDC
VDDO CBP
100 nF
PIP212-12M CBN
VO VSSO VSSC
360 nH 100 F (2x)
DISABLE VCC PWM 1 PWM CONTROLLER PWM 1 PWM 1 PWM 1
10 1 F 1 F
22 F (4x)
VDDG REG5V VI
VDDC
VDDO CBP
100 nF
PIP212-12M CBN
VO VSSO VSSC
360 nH 100 F (2x)
DISABLE
10 1 F 1 F
22 F (4x)
signal ground power ground
VDDG REG5V VI
VDDC
VDDO CBP
100 nF
PIP212-12M CBN
VO VSSO VSSC
360 nH 100 F (2x)
DISABLE
voltage output
03ao41
Fig 10. Typical application circuit using the PIP212-12M in a four-phase converter
A typical four-phase buck converter is shown in Figure 10. This system uses four PIP212-12M devices to deliver a continuous output current of 120 A at an operating frequency of 500 kHz.
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11.2 VDDG supply options
The following options can be used for the lower MOSFET driver supply (VDDG).
conversion supply control circuit supply
5 V external gate drive
VDDG
VDDC
VDDO CBP
100 nF
PWM input
VI
PIP212-12M
CBN Lout VO output
VDDG_EN VSSC
VSSO
Cout
signal ground
power ground
03ar56
Fig 11. Dual supply operation using 5 V external supply for VDDG
conversion supply control circuit supply
VDDG
VDDC
VDDO CBP
100 nF
PWM input open circuit
VI
PIP212-12M
CBN Lout output VO
VDDG_EN VSSC
VSSO
Cout
signal ground
power ground
03ar57
Fig 12. Single supply operation using internal supply for VDDG
conversion supply control circuit supply
VDDG PWM input VI
VDDC
VDDO CBP
100 nF
PIP212-12M
VDDG_EN VSSC
CBN Lout VO output
VSSO
Cout
signal ground
power ground
03ar55
Fig 13. Single supply operation using external supply for VDDG
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12. Marking
terminal 1 index area
TYPE No.
DIFFUSION LOT No.
Design centre k = Hazel Grove, UK Diffusion centre h = Hazel Grove, UK Release status code blank = Released for Supply X = Development Sample Y = Customer Qualification Sample
MANUFACTURING CODE COUNTRY OF ORIGIN
Assembly centre f = Anam Korea
03ao89
hfkYYWWY
Date code YY = last two digits of year WW = week number
03ai72
TYPE No: PIP212-12M-NN (NN is revision number) DIFFUSION LOT No: 7 characters MANUFACTURING CODE; see Figure 15 COUNTRY OF ORIGIN: Korea
Fig 14. SOT684-4 marking
Fig 15. Interpretation of manufacturing code
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13. Package outline
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm
SOT684-4
D D1
B A
terminal 1 index area A E1 E
A4 c A1
detail X
C e1 e 15 L 14
1/2 e
b 28 29
vMCAB wM C
y1 C
y
e Eh1
Eh
1/2 e
e2
Eh2
1 terminal 1 index area 56 Dh1 Dh2 43
42 X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 0.9 A1 0.05 0.00 A4 0.70 0.65 b 0.30 0.18 c 0.2 D 8.1 7.9 D1 7.8 7.7 D h1 2.65 2.35 D h2 3.55 3.25 E 8.1 7.9 E1 7.8 7.7 Eh 6.45 6.15 E h1 3.25 2.95 E h2 2.85 2.55 e 0.5 e1 6.5 e2 6.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
OUTLINE VERSION SOT684-4
REFERENCES IEC --JEDEC MO-220 JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 03-10-23 04-09-14
Fig 16. Package outline SOT684-4 (HVQFN56)
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14. Soldering
14.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
14.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
14.5 Package related soldering information
Table 7: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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DC-to-DC converter powertrain
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
15. Mounting
15.1 PCB design guidelines
The terminals on the underside of the package are rectangular in shape with a rounded edge on the inside. Electrical connection between the package and the printed-circuit board is made by printing solder paste onto the PCB footprint followed by component placement and reflow soldering. The PCB footprint shown in Figure 17 is designed to form reliable solder joints. The use of solder resist between each solder land is recommended. PCB tracks should not be routed through the corner areas shown in Figure 17. This is because there is a small, exposed remnant of the leadframe in each corner of the package, left over from the cropping process. Good surface flatness of the PCB lands is desirable to ensure accuracy of placement after soldering. Printed-circuit boards that are finished with a roller tin process tend to leave small lumps of tin in the corners of each land. Levelling with a hot air knife improves flatness. Alternatively, an electro-less silver or silver immersion process produces completely flat PCB lands.
9397 750 14586
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 -- 2 March 2005
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Philips Semiconductors
PIP212-12M
DC-to-DC converter powertrain
9.25 (2x) 8.30 (2x) 6.20 (2x) 0.475 1.40 0.30 0.50 0.25
1.60 0.45 7.04 (4x) 0.05 0.525
0.40
0.70 (3x)
e = 0.50 0.615 0.80 (2x) 1.90 0.50
0.29 (56x)
solder lands 0.425 7.20 (2x) 9.00 (2x) 0.50 2.00
001aaa064
Cu pattern 0.075 clearance 0.150 solder paste 0.025 placement area
occupied area
All dimensions in mm
Fig 17. PCB footprint for SOT684-4 package (reflow soldering)
15.2 Solder paste printing
The process of printing the solder paste requires care because of the fine pitch and small size of the solder lands. A stencil thickness of 0.125 mm is recommended. The stencil apertures can be made the same size as the solder lands in Figure 17. The type of solder paste recommended for MLF packages is "No clean", Type 3, due to the difficulty of cleaning flux residues from beneath the MLF package.
9397 750 14586
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 -- 2 March 2005
18 of 21
Philips Semiconductors
PIP212-12M
DC-to-DC converter powertrain
16. Revision history
Table 8: Revision history Release date 20050302 Data sheet status Preliminary data sheet Objective data sheet Change notice Doc. number 9397 750 14586 9397 750 14464 Supersedes PIP212-12M_1 Document ID PIP212-12M_2 Modifications: PIP212-12M_1
*
Data sheet status changed to Preliminary data sheet
20041223
9397 750 14586
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 -- 2 March 2005
19 of 21
Philips Semiconductors
PIP212-12M
DC-to-DC converter powertrain
17. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
18. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
20. Trademarks
Intel -- is a registered trademark of Intel Corporation.
19. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14586
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 02 -- 2 March 2005
20 of 21
Philips Semiconductors
PIP212-12M
DC-to-DC converter powertrain
22. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 11.1 11.2 12 13 14 14.1 14.2 14.3 14.4 14.5 15 15.1 15.2 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . 4 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . 4 Boost switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VDDG regulator . . . . . . . . . . . . . . . . . . . . . . . . . 5 3-state function . . . . . . . . . . . . . . . . . . . . . . . . . 5 Automatic Dead-time Reduction (ADR) . . . . . . 5 Over Temperature Protection (OTP) . . . . . . . . . 6 Am I Switching (AIS). . . . . . . . . . . . . . . . . . . . . 6 Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Reg5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal characteristics. . . . . . . . . . . . . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . 11 Typical application. . . . . . . . . . . . . . . . . . . . . . 11 VDDG supply options . . . . . . . . . . . . . . . . . . . . 12 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . 15 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 15 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 16 Package related soldering information . . . . . . 16 Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PCB design guidelines . . . . . . . . . . . . . . . . . . 17 Solder paste printing. . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information . . . . . . . . . . . . . . . . . . . . 20
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 2 March 2005 Document number: 9397 750 14586
Published in The Netherlands

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